The present invention relates to a serial/parallel A/D converter.
With advances in digitization of signal processing in the field of communications and videos and enhancement of performances of video and communication devices, A/D converters as key devices for the digital signal processing are also required to achieve speedup and higher accuracy. As a basic configuration of a high-speed, high-accuracy A/D converter, there is a serial/parallel A/D converter (See U.S. Pat. No. 1,612,640).
Hereinafter, a construction and an operation of a conventional serial/parallel A/D converter will be described with reference to FIGS. 12 and 13.
Initially, the construction of the conventional serial/parallel A/D converter will be described with reference to FIG. 12. FIG. 12 is a diagram illustrating the construction of a conventional four-bit serial/parallel A/D converter.
As shown in FIG. 12, the conventional serial/parallel A/D converter comprises a reference resistor and switch array 12 which are connected between reference voltages 2 and 3, a higher-order voltage comparator array 13 for deciding higher-order two bits, a higher-order code selecting circuit 14 which outputs higher-order code selection signals P0C-P3C on the basis of higher-order voltage comparison results C1C-C3C from the higher-order voltage comparator array 13, a higher-order coding circuit 15 which outputs a two-bit higher-order binary code in accordance with the higher-order code selection signals, a lower-order voltage comparator array 16 for deciding lower-order two bits, a lower-order code selecting circuit 17 which outputs lower-order code selection signals P0F-P3F on the basis of lower-order voltage comparison results C0F-C2F from the lower-order voltage comparator array 16, a lower-order coding circuit 18 which outputs a two-bit lower-order binary code in accordance with the lower-order code selection signals, a code compositing circuit 19 which performs a logic operation on the two-bit higher-order binary code and the two-bit lower-order binary code, thereby to output a four-bit digital signal, and a control signal generating circuit 21 which generates various kinds of control signals for controlling the operational timing of the serial/parallel A/D converter.
The reference resistor and switch array 12 includes a reference resistor 4 that comprises resistors R01-R04, R11-R14, R21-R24, and R31-R34, each having the same resistance value, for dividing the potential between the reference voltages 2 and 3 into 16 equal potentials; and a lower-order reference voltage selection switch 5 that comprises switches S01-S03, S11-S13, S21-S23, and S31-S33 for selecting a lower-order reference voltage, which are provided at positions at which the potential is equally divided into sixteen, respectively.
One input terminal of each voltage comparator 6 constituting the higher-order voltage comparator array 13 is connected to points d1, d2 or d3 at which the potential difference between the reference voltages 2 and 3 of the reference resistor and switch array 12 is divided into four equal potentials, and the other input terminal is connected to an analog input terminal 1. Output terminals of the higher-order voltage comparator array 13 are connected to the higher-order code selecting circuit 14, and output terminals of the higher-order code selecting circuit 14 are connected to input terminals of the higher-order coding circuit 15.
Further, one input terminal of each voltage comparator 6 constituting the lower-order voltage comparator array 16 is connected through the lower-order reference voltage selection switch 5 to the point at which the voltage between the respective points d1, d2 and d3 to which the respective voltage comparators 6 of the higher-order voltage comparator array 13 are connected, is divided into four equal potentials by the reference resistor 4 in the reference resistor and switch array 12, and the other input terminal is connected to the analog input terminal 1. Output terminals of the lower-order voltage comparator array 16 are connected to the lower-order code selecting circuit 17, and output terminals of the lower-order code selecting circuit 17 are connected to the lower-order coding circuit 18.
Output terminals of the higher-order coding circuit 15 and the lower-order coding circuit 18 are connected to the code compositing circuit 19, and a four-bit digital output is obtained from an output terminal of the code compositing circuit 19.
The control signal generating circuit 21 generates various kinds of control signals for controlling the operational timing of the serial/parallel A/D converter, i.e., a sampling signal, a higher-order comparison signal, a lower-order reference voltage decision signal, and a lower-order comparison signal, on the basis of a clock s22 that is input from a clock terminal 22. The sampling signal is input to the respective voltage comparators 6 of the higher-order voltage comparator array 13 and the lower-order voltage comparator array 16, the higher-order comparison signal is input to the higher-order voltage comparator array 13, the lower-order reference voltage decision signal is input to the higher-order voltage comparator array 13, and the lower-order comparison signal is input to the lower-order voltage comparator array 16, respectively. In FIG. 12, these control signals are not shown for the sake of simplification.
Next, the operation of the so-constructed serial/parallel A/D converter will be described with reference to FIG. 13. FIG. 13 is a timing chart illustrating the operation of the conventional serial/parallel A/D converter. In this figure, reference character (a) shows a clock, (b) shows a status of the higher-order voltage comparator array, (c) shows a status of the lower-order voltage comparator array, (d) shows a sampling signal, (e) shows a higher-order comparison signal, (f) shows a lower-order reference voltage decision signal, (g) shows a lower-order comparison signal, (h) shows a status of a lower-order reference voltage, (i) shows an analog input voltage, (j) shows the lower-order reference voltage, and (k) shows an output from the lower-order voltage comparator array. In the construction shown in FIG. 12, there are three lower-order reference voltages and the lower-order voltage comparator array have three outputs, while FIG. 13 shows only one lower-order reference voltage and one output of the lower-order voltage comparator array for the sake of simplification.
Initially, in a sampling period (t1-t2 period), the higher-order voltage comparator array 13 and the lower-order voltage comparator array 16 are simultaneously connected to the analog input terminal 1, and at a falling time of the sampling signal from the control signal generating circuit 21, the respective comparators 6 of the higher-order voltage comparator array 13 and the lower-order voltage comparator array 16 hold an equal analog input voltage Vin of an analog input signal s1 which is input from the analog input terminal 1.
Then, in a higher-order comparison period (t2-t3 period), the respective voltage comparators 6 of the higher-order voltage comparator array 13 compare the analog input voltage Vin which is held in the sampling period, with respective higher-order reference voltages Vr1c, Vr2c and Vr3c which are the voltage values at the points d1, d2 and d3 at which the potential difference between the reference voltages 2 and 3 is divided into four equal potentials. Then, at a falling time of the higher-order comparison signal from the control signal generating circuit 21, the respective voltage comparators 6 of the higher-order voltage comparator array 13 output higher-order voltage comparison results C1C, C2C and C3C as the results of the comparison. Thereafter, the higher-order voltage comparison results C1C, C2C and C3C are inputted to the higher-order code selecting circuit 14, then converted into higher-order code selection signals P0C, P1C, P2C and P3C, and the higher-order coding circuit 15 outputs a two-bit higher-order binary code in accordance with the higher-order code selection signals P0C, P1C, P2C and P3C.
Next, in a lower-order reference voltage decision period (t3-t4 period), at a rising time of the lower-order reference voltage decision signal from the control signal generating circuit 21, an on/off state of the lower-order reference voltage selection switch 5 in the reference resistor and switch array 12 is decided on the basis of the higher-order code selection signals P0C, P1C, P2C and P3C which are output from the higher-order code selecting circuit 14 in the higher-order comparison period, thereby deciding values of lower-order reference voltages Vr1f, Vr2f and Vr3f which are input to the lower-order voltage comparator array 16.
In a lower-order comparison period (t4-t5 period), the respective voltage comparators 6 of the lower-order voltage comparator array 16 compare the analog input voltage Vin which is held in the sampling period, and the lower-order reference voltages Vr1f, Vr2f and Vr3f which are selected by the lower-order reference voltage selection switch 5 of the reference resistor and switch array 12. Then, at a falling time of the lower-order comparison signal from the control signal generating circuit 21, the respective voltage comparators 6 of the lower-order voltage comparator array 16 output lower-order voltage comparison results C0F, C1F and C2F as the results of the comparison. Thereafter, the lower-order voltage comparison results C0F, C1F and C2F are input to the lower-order code selecting circuit 17, then the lower-order code selecting circuit 17 converts these comparison results into lower-order code selection signals P0F, P1F, P2F and P3F, and the lower-order coding circuit 18 outputs a two-bit lower-order binary code in accordance with the lower-order code selection signals P0F, P1F, P2F and P3F. Then, the code compositing circuit 19 performs a logic operation on the two-bit higher-order binary code output from the higher-order coding circuit 15 and the two-bit lower-order binary code output from the lower-order coding circuit 18, thereby outputting a four-bit digital output from a digital output terminal 11.
As described above, according to the conventional serial/parallel A/D converter, initially the respective voltage comparators 6 of the higher-order voltage comparator array 13 and the lower-order voltage comparator array 16 hold the input voltage Vin of the analog input signal s1 which is input from the analog input terminal 1, thereafter the respective voltage comparators 6 of the higher-order voltage comparator array 13 compare the analog input voltage Vin with the higher-order reference voltages Vr1c, Vr2c and Vr3c, then the lower-order reference voltages Vr1f, Vr2f and Vr3f are determined by deciding an on/off state of the lower-order reference voltage switch 5 constituting the reference resistor and switch array 12, on the basis of the higher-order voltage comparison results C1C, C2C and C3C as comparison results, and the respective voltage comparators 6 of the lower-order voltage comparator array 16 compare the determined lower-order reference voltages Vr1f, Vr2f and Vr3f with the analog input voltage Vin which is held in the respective voltage comparators 6 of the lower-order voltage comparator array.
Therefore, according to the conventional serial/parallel A/D converter, as shown in FIG. 13(h), the values of the lower-order reference voltages Vr1f, Vr2f and Vr3f remain held from the period in which the lower-order comparison operation is performed in the lower-order voltage comparator array 16 (t4-t5 period), through a period in which sampling of a next analog input voltage is performed in the higher-order voltage comparator array 13 and the lower-order voltage comparator array 16 (t5-t6 period), to a period in which the higher-order comparison operation is performed in the higher-order voltage comparator array 13 (t6-t7 period). As a result, the on/off state of the lower-order reference voltage selection switch 5 of the reference resistor and switch array 12 for selecting the values of the lower-order reference voltages Vr1f, Vr2f and Vr3f is fixed over the above-mentioned period (t4-t7 period).
When the analog signal s1 which greatly varies between a previous sampling period and the subsequent sampling period as shown in FIG. 13(i) is input to the above-described conventional serial/parallel A/D converter, variation in the values of the lower-order reference voltages Vr1f, Vr2f and Vr3f is also increased as shown in FIG. 13(j), resulting in a longer transition time from when the lower-order reference voltages change to when the lower-order reference voltages are stabilized at new values. However, since the on/off state of the lower-order reference voltage selection switch 5 of the reference resistor and switch array 12 is fixed until the lower-order reference voltage decision period, when the conventional serial/parallel A/D converter is operated at a high speed, the operation shifts from the lower-order reference voltage decision period (e.g., t7-t8 period in FIG. 13) to the lower-order comparison period (t8-t9 period) before the lower-order reference voltages Vr1f, Vr2f and Vr3f change in voltage values and are stabilized at new values, whereby the respective voltage comparators 6 of the lower-order voltage comparator array 16 unfavorably start the comparison operation of the analog input voltage Vin with pre-stabilization lower-order reference voltages (see FIG. 13(j)).
As a result, as shown in FIG. 13(k), the respective voltage comparators 6 of the lower-order voltage comparator array 16 initially judge that the analog input voltage Vin is larger than the lower-order reference voltage, and then judge that the lower-order reference voltage is larger than the analog input voltage Vin, resulting in a deteriorated accuracy of output from the lower-order voltage comparator array 16, which prevents speedup and improvement in accuracy of the serial/parallel A/D converter.
The present invention has for its object to provide a serial/parallel A/D converter which is capable of performing a high-speed and high-accuracy operation even when an analog input voltage Vin greatly varies between a sampling period in which the analog input voltage Vin is held and the subsequent sampling period, and an A/D conversion method for the serial/parallel A/D converter.
Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the scope of the invention will be apparent to those of skill in the art from the detailed description.
According to a 1st aspect of the present invention, there is provided an A/D conversion method for a serial/parallel A/D converter which compares an analog input voltage which randomly varies with time and a prescribed first reference voltage, to generate a first binary code, as well as compares a second reference voltage which is decided on the basis of the result of the comparison and the analog input voltage, to generate a second binary code, and performs a logic operation on the generated first and second binary codes, thereby generating a digital value, said method comprising: a sampling and initialization step of sampling the analog input voltage received, as well as initializing a previous second reference voltage to a prescribed initialization voltage; a first voltage comparison step of comparing the value of the analog input voltage which has been sampled in the sampling and initialization step and the first reference voltage, to generate the first binary code; and a second voltage comparison step of comparing the value of the second reference voltage which has been changed from the prescribed initialization voltage to a voltage which is decided on the basis of the result of the comparison in the first voltage comparison step, with the analog input voltage which has been sampled in the sampling and initialization step, to generate the second binary code. Therefore, a previous second reference voltage can be initialized to a prescribed initialization value while the analog input voltage is sampled, and in the second voltage comparison step, the value of the second reference voltage can be changed from the prescribed initialization voltage to a value which is decided on the basis of the result of the comparison between the first reference voltage and the sampled analog input voltage. As a result, even when the analog input voltage greatly varies in a period between sampling of the analog input voltage and sampling of a next analog input voltage, the amount of changes of the second reference voltage in the second voltage comparison step can be reduced, whereby the AD conversion can be performed at a high speed and high accuracy.
According to a 2nd aspect of the present invention, there is provided an A/D conversion method for a serial/parallel A/D converter which compares an analog input voltage which randomly varies with time and a prescribed first reference voltage, to generates a first binary code, as well as compares a second reference voltage which is decided on the basis of the result of the comparison, and the analog input voltage, to generates a second binary code, and performs a logic operation on the generated first and second binary codes, thereby generating a digital value, said method comprising: a sampling step of sampling the analog input voltage received; a first voltage comparison and initialization step of comparing the analog input voltage which has been sampled in the sampling step and the first reference voltage, and initializing a previous second reference voltage to a prescribed initialization voltage, to generate the first binary code; and a second voltage comparison step of comparing the second reference voltage which has been changed from the prescribed initialization voltage to a voltage value which is decided on the basis of the result of the comparison in the first voltage comparison and initialization step, and the analog input voltage which has been sampled in the sampling step, to generate the second binary code. Therefore, a previous second reference voltage can be initialized to a prescribed initialization value while the first reference voltage is compared with the sampled value of the analog input voltage, and in the second voltage comparison step, the value of the second reference voltage can be changed from the prescribed initialization voltage to a value which is decided on the basis of the result of the comparison between the first reference voltage and the sampled analog input voltage value. As a result, even when the analog input voltage greatly varies in a period between sampling of the analog input voltage and sampling of a next analog input voltage, the amount of changes of the second reference voltage in the second voltage comparison step can be reduced, whereby the AD conversion can be performed at a high speed and high accuracy. Further, since the previous second reference voltage is initialized to the prescribed initialization voltage while the value of the first reference voltage is compared with the sampled value of the analog input voltage, the value of the second reference voltage is held at the sampling of the analog input voltage and would not be changed, whereby a stable sampling operation can be performed without being affected by noises that are caused by the change of the second reference voltage.
According to a 3rd aspect of the present invention, there is provided an A/D conversion method for a serial/parallel A/D converter which compares an analog input voltage which randomly varies with time and a prescribed first reference voltage, to generate a first binary code, as well as repeatedly compares a reference voltage which is decided on the basis of the result of the comparison and the analog input voltage to generate a binary code, thereby generating second to n-th (xe2x80x9cnxe2x80x9d is an integer satisfying nxe2x89xa73) binary codes, and performs a logic operation on the generated first to n-th binary codes, thereby generating a digital value, said method comprising steps of: sampling the analog input voltage received, as well as initializing previous second to n-th reference voltages to a prescribed initialization voltage; and carrying out an m-th voltage comparison step (xe2x80x9cmxe2x80x9d is an integer satisfying 1xe2x89xa6m less than n) of comparing the value of the analog input voltage which has been sampled in the sampling and initialization step and the m-th reference voltage, to generate the m-th binary code, and an (m+1)-th voltage comparison step of comparing the value of the (m+1)-th reference voltage which has been changed from the prescribed initialization voltage to a voltage value which is decided on the basis of the result of the comparison in the m-th voltage comparison step and the value of the analog input voltage which has been sampled in the sampling and initialization step, to generate the (m+1)-th binary code, from m=1 to m=nxe2x88x921. Therefore, a previous (m+1)-th reference voltage can be initialized to a prescribed initialization value while the analog input voltage is sampled, and in the (m+1)-th voltage comparison step, the value of the (m+1)-th reference voltage can be changed from the prescribed initialization voltage to a value which is decided on the basis of the result of the comparison between the m-th reference voltage and the sampled analog input voltage. As a result, even when the analog input voltage greatly varies in a period between the sampling of the analog input voltage and sampling of a next analog input voltage, the amount of changes of the (m+1)-th reference voltage in the (m+1)-th voltage comparison step can be reduced, whereby AD conversion can be performed at a high speed and high accuracy.
According to a 4th aspect of the present invention, there is provided an A/D conversion method for a serial/parallel A/D converter which compares an analog input voltage which randomly varies with time and a prescribed first reference voltage, to generate a first binary code, as well as repeatedly compares a reference voltage which is decided on the basis of the result of the comparison and the analog input voltage to generate a binary code, thereby generating second to n-th (xe2x80x9cnxe2x80x9d is an integer satisfying nxe2x89xa73) binary codes, and performs a logic operation on the generated first to n-th binary codes, thereby generating a digital value, said method comprising steps of: sampling the analog input voltage received; and carrying out an m-th voltage comparison and initialization step (xe2x80x9cmxe2x80x9d is an integer satisfying 1xe2x89xa6m less than n) of comparing the value of the analog input voltage which has been sampled in the sampling step and the m-th reference voltage, as well as initializing a previous (m+1)-th reference voltage to a prescribed initialization voltage, to generate the m-th binary code, and an (m+1)-th voltage comparison step of comparing the value of the (m+1)-th reference voltage which has been changed from the prescribed initialization voltage to a voltage value which is decided on the basis of the result of the comparison in the m-th voltage comparison and initialization step and the value of the analog input voltage which has been sampled in the sampling step, to generate the (m+1)-th binary code, from m=1 to m=nxe2x88x921. Therefore, a previous (m+1)-th reference voltage can be initialized to a prescribed initialization value while the m-th reference voltage is compared with the sampled analog input voltage, and in the (m+1)-th voltage comparison step, the value of the m-th reference voltage can be changed from the prescribed initialization voltage to a value which is decided on the basis of the result of the comparison between the m-th reference voltage and the sampled analog input voltage. As a result, even when the analog input voltage greatly varies in a period between the sampling of the analog input voltage and sampling of a next analog input voltage, the amount of changes of the (m+1)-th reference voltage in the (m+1)-th voltage comparison step can be reduced, whereby the AD conversion can be performed at a high speed and high accuracy. Further, since the previous (m+1)-th reference voltage is initialized to the prescribed initialization voltage while the m-th reference voltage is compared with the sampled analog input voltage, the value of the (m+1)-th reference voltage is held at the sampling of the analog input voltage and would not be varied, whereby a stable sampling operation can be performed without being affected by noises that are caused by the change of the (m+1)-th reference voltage.
According to a 5th aspect of the present invention, there is provided a serial/parallel A/D converter for converting an analog input voltage into a digital value, comprising: a reference resistor and switch array which is constituted by a resistor array comprising plural resistors which are serially connected, and plural switches connected to plural connection points of the resistor array, for selectively outputting a reference voltage which is compared with the analog input voltage that randomly varies with time; a first voltage comparator array for sampling the analog input voltage received, and comparing the sampled analog input voltage and a first reference voltage which is output from the reference resistor and switch array, to output a first comparison result; a first code selecting circuit which receives the first comparison result output from the first voltage comparator array, and outputs a first code selection signal; a first coding circuit which outputs a first binary code that is selected in accordance with the first code selection signal output from the first code selecting circuit; a second voltage comparator array for sampling the analog input voltage received, and comparing the sampled analog input voltage and a second reference voltage which is selectively output by the plural switches constituting the reference resistor and switch array in accordance with the first code selection signal, to output a second comparison result; a second code selecting circuit which receives the second comparison result output from the second voltage comparator array, and outputs a second code selection signal; a second coding circuit which outputs a second binary code which is selected in accordance with the second code selection signal output from the second code selecting circuit; and a code compositing circuit which performs a logic operation on the first binary code and the second binary code, to obtain a digital value, in which the second voltage comparator array samples the received analog input voltage, receives and holds a prescribed initialization voltage in an arbitrary period of time, and compares the value of the second reference voltage which has been changed from the prescribed initialization voltage to a voltage value which is selectively output by the plural switches constituting the reference resistor and switch array in accordance with the first code selection signal, and the value of the sampled analog input voltage. Therefore, the second reference voltage can be initialized to a prescribed voltage value in an arbitrary period from the start of the sampling of the analog input voltage to the comparison for the second reference voltage. As a result, even when the analog input voltage greatly varies in a period between the sampling of the analog input voltage and sampling of a next analog input voltage, the amount of variations of the second reference voltage can be reduced, thereby realizing a serial/parallel A/D converter which is operable at high speed with high accuracy.
According to a 6th aspect of the present invention, in the serial/parallel A/D converter of the 5th aspect, the initialization voltage is a reference voltage which is output from one of the plural connection points of the resistor array constituting the reference resistor and switch array. Therefore, the serial/parallel A/D converter is not required to have a prescribed voltage to which the second reference voltage is initialized, thereby simplifying the construction of the serial/parallel A/D converter.
According to a 7th aspect of the present invention, the serial/parallel A/D converter of the 5th aspect further includes a reference voltage initializing circuit which receives the second reference voltage output from the reference resistor and switch array, the initialization voltage, and an initialization control signal indicating the arbitrary period, and outputs either the second reference voltage or the prescribed voltage to the second voltage comparator array in accordance with the initialization control signal, and the reference voltage initializing circuit outputs the initialization voltage in the arbitrary period, while outputting the second reference voltage which is output from the reference resistor and switch array in periods other than the arbitrary period. Therefore, the second reference voltage can be initialized to a prescribed voltage value in an arbitrary period, and the prescribed voltage value can be changed to a voltage value which is selectively output on the basis of the first comparison result. As a result, even when the analog input voltage greatly varies in a period between the sampling of the analog input voltage and sampling of a next analog input voltage, the amount of variations of the second reference voltage can be reduced, thereby realizing a serial/parallel A/D converter which is operable at a high speed with high accuracy.
According to an 8th aspect of the present invention, in the serial/parallel A/D converter of the 5th aspect, the first code selecting circuit receives an initialization control signal indicating the arbitrary period, as well as the first comparison result output from the first voltage comparator array, and in the arbitrary period, the first code selection signal is output to the first coding circuit, as well as an initialization voltage selection signal for selecting the prescribed initialization voltage by fixing predetermined switches among the plural switches constituting the reference resistor and switch array in on-state while fixing all other switches in off-state is output to the reference resistor and switch array, and in periods other than the arbitrary period, the first code selection signal is output to the first coding circuit and the reference resistor and switch array. Therefore, the second reference voltage can be initialized to a prescribed voltage value in an arbitrary period without the need for adding any new components to the serial/parallel A/D converter, whereby the construction of the serial/parallel A/D converter which is operable at a high speed with high accuracy can be more simplified.
According to a 9th aspect of the present invention, in the serial/parallel A/D converter of the 5th aspect, the arbitrary period is a period during which the analog input voltage input is sampled in the first and second voltage comparator arrays. Therefore, the second reference voltage can be initialized to a prescribed voltage value in the period when the analog input voltage is held, thereby realizing the serial/parallel A/D converter which is operable at a high speed with high accuracy.
According to a 10th aspect of the present invention, in the serial/parallel A/D converter of the 5th aspect, arbitrary period is a period during which the first voltage comparator array compares the analog voltage value and the first reference voltage which is output from the reference resistor and switch array, and outputs the first comparison result. Therefore, the value of the second reference voltage is held at the sampling of the analog input voltage and would not be varied, whereby a stable sampling operation can be performed without being affected by noises that are caused by the change of the second reference voltage.
According to an 11th aspect of the present invention, there is provided a serial/parallel A/D converter for converting an analog input voltage into a digital value, comprising: a reference resistor and switch array which is constituted by a resistor array comprising plural resistors which are serially connected, and plural switches connected to plural connection points of the resistor array, for selectively outputting a reference voltage which is compared with the analog input voltage that randomly varies with time; a first voltage comparator array for sampling the analog input voltage received, and comparing the sampled analog input voltage and a first reference voltage which is output from the reference resistor and switch array, to output a first comparison result; second to n-th voltage comparator arrays for sampling the analog input voltage received, and comparing the sampled analog input voltage and second to n-th reference voltages which are generated in the reference resistor and switch array on the basis of comparison results from the first to (nxe2x88x921)-th (xe2x80x9cnxe2x80x9d is an integer satisfying nxe2x89xa73) voltage comparator arrays, respectively, to output second to n-th comparison results, respectively; first to n-th code selecting circuits which receive the first to n-th comparison results output from the first to n-th voltage comparator arrays, respectively, and output first to n-th code selection signals, respectively; first to n-th coding circuits which output first to n-th binary codes that are selected in accordance with the first to n-th code selection signals output from the first to n-th code selecting circuits, respectively; and a code compositing circuit which performs a logic operation on the first to n-th binary codes output from the first to n-th coding circuits, to obtain a digital value, in which each of said second to n-th voltage comparator arrays samples the analog input voltage, receives and holds a prescribed initialization voltage in an arbitrary period of time, and compares each value of the second to n-th reference voltages which has been changed from the prescribed initialization voltage to a voltage value that is selectively output by the plural switches constituting the reference resistor and switch array adaptively to the respective first to (nxe2x88x921)-th code selection signals, with the value of the sampled analog input voltage. Therefore, the second to n-th reference voltages can be initialized to a prescribed voltage value in an arbitrary period from the start of the sampling of the analog input voltage to the comparison for the second to n-th reference voltages. As a result, even when the analog input voltage greatly varies in a period between the holding of the analog input voltage and holding of a next analog input voltage, the amount of variations of the second to n-th reference voltages can be reduced, thereby realizing a serial/parallel A/D converter which is operable at high speed with high accuracy.